1. Field of the Invention
The present invention relates to a variable length decoder having a reduced chip size made possible by decreasing the size of the output data and simultaneously enabling effective input/output data processing.
2. Discussion of the Related Art
Two popular international standards, JPEG (Joint Picture Experts Group) or MPEG (Moving Picture Experts Group) of the video compression art represent video signals using the DCT (Discrete Cosine Transform).
The video information of each pixel block, i.e. the variations of luminance and chrominance, is negligible through the whole picture in general video signals. However, the coefficients of the DCT (Discrete Cosine Transform) of the video signals are distributed unevenly, i.e., are decorelated, to the low portion of the spatial frequency after transformation. Accordingly, the information compression is achieved by retaining the low frequency portion (including most of the information necessary for restoring the video information) but discarding the high frequency portion. That is the major reason why DCT is used in JPEG or MPEG.
The average length of the symbol can be reduced when establishing a new symbol system (or codebook) between a decoder and an encoder by allotting a short length symbol to the high probability transform coefficients and allotting a long length symbol to the low probability transform coefficients. Implementation of such a codebook is achieved by a Variable Length Encoder and a corresponding Variable Length Decoder. Thus, the length of each unit data block processed in the variable length decoder and encoder becomes variable as well.
FIG. 1 shows the block diagram of a variable length decoder according to a related art.
Referring to FIG. 1, a variable length decoder has an input buffer 10, an output buffer 70, a programmable logic array 60 for decoding data and a variable block for varying the data length to be transferred from the input buffer 10 to the programmable logic array 60. The variable block consists of a pair of latches 20 and 30, a 32 bit barrel shifter 40 and an accumulator 50.
Encoded data outputted from a variable length encoder is inputted to the input buffer 10. The data stored in the input buffer 10 is accessed by the latch 20 in units of 16 bits according to a latch enabling signal L. The data stored in the latch 20 is also transferred to the other latch 30 under the control of the latch enabling signal L. Together the latches 20 and 30 hold 32 bits of data.
The barrel shifter 40, into which 32 bits of data are inputted, has a 4 bit shift pointer and a 16 bit output. The upper 16 bits of data in the barrel shifter 40 come from the latch 20 while the lower 16 bits of data in the barrel shifter 40 come from the other latch. The shift pointer S indicates the initial bit of the valid data. A length of 4 bits is enough for the length of the shift pointer S since the maximum number of bits transferred at one instance the from the barrel shifter 40 to the logic array 60 are 16. Such a shift pointer S is supplied from the accumulator 50.
The accumulator 50 has a binary value of 0000 as an initial value for the shift pointer, into which word length W of 4 bits from the programmable logic array 60 is inputted. Accordingly, a new word length W is accumulated in the shift pointer S where the previous value had been stored. The result of the accumulation is outputted as the shift pointer S of the barrel shifter 40. The carry output, C, of the accumulator generates the latch enabling signal, L. Once the carry output, C, of the accumulator goes to a logical high state, i.e. C=1, the data of the input buffer 10 is accessed by the latch 20 and data is shifted from the latch 20 to the latch 30.
The programmable logic array 60 restores, i.e. decodes, the data that has been encoded by the variable length encoder. The restored data is transmitted to the output buffer 70 to be stored.
In the variable length encoder, the data from the input buffer 10 is accessed by the latch 20 and shifted from the latch 20 latch 30 every time the latch enabling signal L takes the logic value 1 to fill the latches 20 and 30 with data under the control of the accumulator 50. The latch enabling signal L will take the logic value 1 three times if the length of the data to be read from the input buffer 10 is 24 bits. Thus, for each 16 bits of desired data in the input buffer 10, the latches 20 and 30 must be latched.
Moreover, the size of the programmable logic array 60 must be increased by 16 bit increments since the programmable logic array 60 needs a circuit large enough to deal with the 16 bit units of data received from the barrel shifter 40.